Date:2025.05.27
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Silicon Carbide (SiC) MOSFETs have emerged as game-changers in power electronics due to their wide bandgap,enabling them to handle significantly higher voltages and temperatures than traditional silicon devices. With a critical electric field nearly an order of magnitude higher, SiC allows for a much thinner, highly doped drift layer, resulting in lower on-resistance and higher efficiency with less wasted heat. Additionally, SiC's thermal conductivity is over three times greater, which helps in spreading heat more effectively and supports faster switching speeds that make these devices ideal for industrial motor drives, renewable energy inverters,and electric vehicle powertrains. However, in critical automotive and aerospace systems, it's not enough for a device to perform well but must also be exceptionally reliable. In this article, we explore the primary reliability challenges of SiC MOSFETs, focusing on the root causes, failures mechanism and WLBI technique for screeing.
In examining the reliability of the SiC MOSFET, engineers tend to separate it into extrinsic failure and intrinsic failure in order to identify the exact root causes of the failure. Thus, it's a good refreshment for us to understand the term of both extrinsic and intrinsic failures. Extrinsic failure commonly referring to the failures that related with the manufacturing process and material defects. It also known as early life failure or infant mortality. On the other hands, intrinsic failures are due to the wear out issue after the aging operation. It's a natural behaviour that degrade the device performance after the long operation [1].
Although SiC MOSFET is widely adopted in different power semiconductor and automotive industry, engineers still facing a lot of extrinsic failures that linked to the challenges of newer materials and processes. Among of these, gate oxide defects due to the tiny imperfections in the gate dielectric are the major cause of the infant mortality. During the fabrication, microscopic contaminants or crystal defects may embedded inside the SiO₂ gate oxide. These inclusions act as local weak spots causing the oxide layer thinner. As a result, the electric field will concentrate at these local weak spots and reduce the dielectric strength which will degrade the reliability of gate voltage [2]. Figure 1 illustrates how's the extrinsic oxide defects create a "thinning" effect in the dielectric. Besides that, Basal Plane Dislocations (BPD) and stacking faults in the crystal lattice also contribute to the extrinsic failure. These are the crystallographic defects that originate from the wafer or epitaxial growth. Electron-hole pair recombination that happened at BPD under the bipolar current flow will induce the stacking faults which eventually degrading the device performance [3]. For instance, a BPD that propagates into the device's active area can locally distort electric fields or causing charge recombination behaviour. If such a dislocation lies in a critical region, it can trigger device failure under high voltage or current stress. Lastly, process-induced defect like ion implantation or metallization also another critical aspect that causing the extrinsic failure. High temperature implantation process was needed to form the p-well (body) and other regions in SiC MOSFET fabrication. Study [4] showing that deep implantation in certain SiC MOSFET designs led to BPDs forming in the drift layer, which then caused reliability issues in those devices [4].
Figure 1: The potential “thinning” effects causing extrinsic failures.
After screening through the infant mortality which related to extrinsic failure, intrinsic failures start to dominate due to the aging usage which representing at the tail end of the reliability bathtub curve. There're 2 intrinsic reliability concerns for SiC MOSFET including gate oxide wear-out and body diode degradation. Every SiC MOSFET will have a finite lifetime under dielectric stress and continuous operation may lead to time-dependent dielectric breakdown (TDDB). Technically, the oxide accumulates charge traps which will degrading the performance gradually until it breaks down. This degradation is exacerbated by SiC's material properties: its wide bandgap lowers the barrier for electron tunnelling into SiO₂, making it more susceptible to leakage currents that slowly deteriorate the oxide layer [5]. On the other hand, body diode degradation that linked to stacking faults also will deteriorates the device performance over the time. The body diode in a MOSFET was formed by the p-n junction between the p-body and n-drift. The minority carries will injecting into the drift region when the diode is in conduction state. And, the crystal defects can transform and grow in this state, causing a permanent increase in forward voltage over time. Specifically, a basal plane dislocation can expand into a larger stacking fault during forward current conduction which is a phenomenon not seen in silicon devices [4]. Practically, it's hard to define a clear boundary between the extrinsic and intrinsic failures as one may correlated to the other. For instance, BPD is an extrinsic defect but the triggered failure like stacking fault expansion can be occurred during aging operation. Hence, understanding the failure mechanism also very important for the engineer to improve the reliability of the devices.
In a SiC MOSFET, the gate oxide with typically ~50nm of SiO₂ is often the weak link as it must withstand high electric fields from the combination of the gate bias and the large drain voltage. Over time,the failure mechanisms can occur in the oxide under high electric field stress which are charge trapping and eventually dielectric breakdown. Charge trapping happens when a positive bias was applied to the gate terminal. The electrons from the SiC channel are attracted toward the SiO₂ layer which the oxide may insulates it under normal condition. The SiC MOSFET tends to has higher field which typically in the range of 4-6MV/cm corresponding to 15-20V gate voltage range for a typical oxide thickness. This behaviour will cause a small fraction of electrons can overcome the barrier and tunnel into the oxide by the Fowler–Nordheim (FN) mechanism [5]. Each tunnelling electron can become trapped in the oxide or at the SiC/SiO₂ interface, leaving behind a charged defect. Over millions of field cycles or hours of bias,these trapped charges are accumulated and shift the device's threshold voltage. Moreover, they create localized stress that weakens the oxide's molecular structure which led to total device failure. It's also worth noting that oxide thinning effects play a role too. If certain regions of the gate oxide are thinner (due to the extrinsic defects mentioned earlier), the electric field in those spots will be higher and tends to have early breakdown.
Another typical failure mechanism is the body diode degradation. SiC MOSFETs carry an intrinsic body diode which is the p–n junction between the MOSFET's p-body of source region and the n-drain. This diode conducts current when the MOSFET is reverse-biased and the channel is off, as often happens in half-bridge circuits during the "freewheeling"period. Ideally, the body diode provides a convenient path for current with behave similar to an external diode. However, in SiC MOSFET, this PN diode conduction can lead to carrier-induced stacking fault expansion. The issue originates from the pre-existing BPD in the SiC crystal as we discussed earlier. The recombination of electrons and holes during bipolar operation releases energy that causes stacking faults to expand along the BPD, eventually growing to the chip's surface where they stop developing, rendering the affected areas (as shown in Figure 2) non-conductive and thereby reducing the chip's effective active area [2]. The immediate effect of this defect growth is an increase in the diode's forward voltage. With the same current flows through a smaller effective area of the diode, the current density is higher and the diode drop increases. This phenomenon is often called forward voltage drift or bipolar degradation. For example, if a SiC MOSFET body diode initially had a forward drop of 3 V at a certain current, after extended conduction it might require 3.3 V to carry that current.
Figure 2: Top view and cross section of stacking fault in a SiC devices [2].
Due to the extrinsic defects are a primary cause of early failures, manufacturers put a lot of effort into screening SiC MOSFETs for those weak devices before they ship it. One of the most effective approaches is performing a wafer-level burn-in (WLBI). By applying accelerated stress tests during the burn in to the dies on the wafer, in order to catch any latent defects. By weeding out bad die at wafer level, companies can deliver only the robust die to assembly, greatly improving reliability in the field. Two common stress tests used in both device qualification and production screening are High-Temperature Gate Bias (HTGB) and High-Temperature Reverse Bias (HTRB). These tests, often run for several hours at elevated conditions, are designed to simulate years of electrical stress in a short time, forcing early failures to occur in the lab rather than in customer applications.
This test specifically targets the gate oxide integrity and stability. In HTGB, the MOSFETs are heated to a high temperature (typically 150–175 °C) and a constant voltage (usually the maximum rated gate voltage, e.g. +15 V or +20 V) is applied to the gate while the source and drain are shorted together as illustrated in Figure 3. Essentially, the device is held on at high temperature for an extended time. During HTGB, gate leakage current (Igss) is monitored, as well as any shifts in threshold voltage. The high thermal energy accelerates charge trapping and defect activation in the gate oxide. If a device has a marginal gate oxide (say a thin spot or impurities), the stress can cause its leakage to rise or an abrupt breakdown to occur. HTGB can also reveal devices prone to threshold voltage instability where oxide traps cause threshold voltage to drift under bias. By the end of an HTGB burn-in, any MOSFET with abnormal gate leakage or large threshold voltage shifts is flagged as a failed device. This test thereby screens out units that would have likely suffered gate oxide failure in the field
Figure 3: The schematic diagram for HTGB burn-in test.
This test stresses the MOSFET's drift region and junctions under high voltage. In HTRB, devices are again heated (150–175 °C), and a high DC voltage (typically 80% of the device's rated drain-to-source breakdown voltage) is applied from drain to source while the gate is held off (0 V or a slight negative bias) as shown in Figure 4. Over the burn-in duration, the drain leakage current (Idss) is monitored. HTRB effectively puts the device in a worst-case off-state condition in which a hot device sustaining a large electric field across the epitaxial drift layer and junctions. Any localized defects – for instance, a residual dislocation or implant damage site that creates a micro-leakage path will tend to show up as an increase in Idss or an unstable leakage that grows with time at elevated temperature. In some cases, HTRB can induce a catastrophic breakdown if a device has a severe defect. More commonly, it identifies devices with excessive leakage or soft breakdown behaviour which would be units prone to failing under high-voltage operation. HTRB thus flushes out devices with drift-region defects, poor edge terminations, or other flaws that could lead to insulation failure.
Figure 4: The schematic diagram for HTRB burn-in test.
In conclusion, the reliability of SiC MOSFETs is crucial for high-power applications and automotive industry. An effective screening is essential to overcome the SiC reliability issue and improve the overall yield. Semight Instruments WLBI instruments series provide a cutting-edge solution by integrating HTGB, HTRB, and Vth testing in a single probing touchdown, significantly improving efficiency and test accuracy. By aligning with the industry standards, WLBI3800 series for example enhances device screening, reduces infant mortality, and ensures long-term operational stability.
1. Wolfspeed, "A Designer'Guide to Silicon Carbide: Quality, Qualification, and Long-Term Reliability"
2. Infineon Technologies White Paper, "How Infineon assures the reliability of SiC power semiconductors"
3. V. Veliadis et al., "Impact of Basal Plane Dislocations and Ruggedness of 10 kV 4H-SiC Transistors", 11th International MOS-AK Workshop, 2018
4. Jiashu Qian et al., "An Investigation of Body Diode Reliability in Commercial 1.2 kV SiC Power MOSFETs with Planar and Trench Structures", MDPI, 2024
5. Singh, R. and Hefner Jr. A., "Reliability of SiC MOS Devices", Journal of Solid-state Electronics, 2024
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