Abstract

WAT is a cornerstone of semiconductor manufacturing, ensuring that wafers meet the highest standards of quality, reliability, and performance. Test structures are designed in on the wafer (usually in the scribe line) to provide critical insights into the quality of the fabrication process; WAT helps manufacturers to improve yields, reduce costs, and deliver cutting-edge technologies to the market.

As the industry continues to advance, WAT will remain an indispensable tool during product launch and for maintaining the integrity of semiconductor production.

1.   Introduction

Objectives of the paper:

Explaining Wafer Acceptance Test (WAT) and the importance of it in the semiconductor industry

WAT or sometimes also referred to as parametric testing is an important process control step during the manufacturing of wafers. The goal is to ensure that the wafer production process is consistent and to maximize yields.

The idea of WAT is not new, already in 1997/1978 Taiwan Semiconductor Manufacturing Company Limited (TSMC) filed patents for “Integrated defect yield management and query system“ and “Automatic wafer acceptance test method”. The importance of these tests as part of the process control during wafer manufacturing has not changed since then, it is a very important tool in the process control chain.

These days the standard approach for WAT is to add special test structures, usually in the scribe line – or the area between the dies. These so-called monitors are there to be measured, in a non-destructive way, and the data is used to control and verify the manufacturing process. Therefore, WAT is part of the Process Control Monitoring (PCM). The selected test methods are designed for structural testing and therefore performed as step of the wafer manufacturing process.

2.  The importance of WAT in ensuring wafer quality and yield

WAT data is generated by the wafer fab at the end of the manufacturing process. This testing is the wafers initial measurement to confirm the structural integrity from the growing process. As data is very limited, it becomes difficult to evaluate and analyze the PCM and the WAT data is an essential tool to forecast any issues or failure that may arise in the later process.

WAT therefore is not only a PCM for production but also one of the most important tools for Engineering during the development of a new product. Extensive engineering WAT test structures can help identify failure and issues that will impact the yield and create operational inefficiencies.

The production WAT data is generally made available to the fabless customer for every shipped wafer.

Consistency in the semiconductor manufacturing process is the goal to avoid loosing millions of dollars in earnings through yield loss.

                         Figure  1 - Wafer with WAT sites indicated

3.Detailed Overview of Wafer Acceptance Test (WAT)

This chapter provides a detailed overview of WAT, including the typical key parameters tested, the test structures used, and the variations encountered during the testing process.

 Typical Key Parameters and Test Structures

WAT focuses on measuring a range of electrical and physical parameters to ensure the wafer meets design specifications and process requirements.

Resistance / Resistors:

Used to measure sheet resistance and contact resistance.

Capacitance / Capacitors:

Designed to evaluate capacitance and dielectric integrity.

Leakage Current / Diodes:

Used to assess junction properties and leakage current.

Ids (Drain-to-Source Current) / Transistors:

Provide data on key transistor parameters such as Ids current, threshold voltage, and gate oxide integrity.

These test structures are strategically distributed across the wafer to capture variations in process uniformity. For example, structures are placed at the edge, center, and intermediate positions (left, right, up, down) of the wafer, as illustrated in Figure 1. This distribution helps identify spatial variations in the fabrication process.

Figure  2 - Position of the WAT Test Structure in the scribe line

WAT Variations and their interpretation

WAT data must be distinguished between local variations and global variations. By analyzing these variations, manufacturers can pinpoint the root causes of defects and assess whether they are isolated to specific regions or indicative of systemic issues. This differentiation is crucial for implementing targeted process optimizations and maintaining uniformity across the entire production line.

Local Variations

Local variations refer to differences within a single die or small regions of the wafer. These can arise from lithography or etching inconsistencies.

Local variations are particularly critical in advanced technologies, where even minor deviations can significantly impact device performance.

Global Variations

Global Variations refer to differences at wafer-to-wafer or lot-to-lot data. These can identify equipment drift or process instability.

Special Considerations for Wide Bandgap Materials (e.g., SiC)

With the rise of wide bandgap materials like Silicon Carbide (SiC), WAT faces new challenges and requirements, in special regarding High Voltage Testing. SiC devices operate at high voltages (up to 3500V), therefore require specialized equipment to test breakdown voltage and leakage current.

4.WAT Methodology

The Prober is handling the wafer, similar to chip probe / wafer die test.

To perform the wafer acceptance tests different instrumentation will used to provide the required current versus voltage (IV) and capacitance versus voltage (CV) measurements, this typically includes Source/Measure Units (SMUs), precision digital voltmeters, pulse generators and capacitance meters.

Thes will all be connected via a switch matrix (High-voltage Low-leakage Switch Matrix for SiC) to the test points on the wafer.

For this a Probe Card and a traditional Pogo Tower are used in the setup.

Figure  3 - Typical WAT Setup

5.Challenges in WAT

The challenges these days come from two directions; there is the trend for lower current measurements, which requires longer settling times due to the capacitive effects of cable insulation. This is especially critical if the test flow requires the applied voltage to be swept, as this parasitic capacitance will draw a charging current. The other trend is driven mainly by the automotive EV industry and SiC or other wide-bandgap devices. Equipment is required that is capable of providing high voltages and currents for accurate testing.

6.Future Trends and Innovations

To further improve WAT and the impact to Cost of Test (CoT), we will likely see more advanced array test structures implemented.

Figure 4 - Conventional Test Structures

The move from these Conventional Test Structures (Figure 4 - Conventional Test Structures) to Array Test Structures (Figure 5 - Array Test Structures) will bring multiple benefits, like reduced test time, enhanced PCM data, improved scalability and more.

Figure 5 - Array Test Structures